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Chapter 3: Design Rules and Procedures
3–9
Frequency Design Rules
For Simulink simulation, all DSP Builder blocks (including registered DSP Builder
blocks) use the sampling period specified in the Clock block. If there is no Clock block
in your design, the DSP Builder blocks use a sampling frequency of 1. You can use the
Clock block to change the Simulink sample period and the hardware clock period.
Multiple Clock Domains
A DSP Builder model can operate using multiple Simulink sampling periods. You can
specify the clock domain in some DSP Builder block sources, such as the Counter
block. You can also specify the clock domain in DSP Builder rate change blocks such
as Tsamp .
When using multiple sampling periods, DSP Builder must associate each sampling
period to a physical clock domain that can be available from an FPGA PLL or a clock
input pin. Therefore, the top-level DSP Builder model must contain DSP Builder rate
change blocks such as PLL or Clock_Derived .
You can use a PLL block to synthesize additional clock signals from a reference clock
signal. These internal clock signals are multiples of the system clock frequency.
f Refer to “Using the PLL Block” on page 3–14 for more information.
If your design contains the PLL block, Clock or Clock_Derived blocks, the DSP Builder
registered blocks operate on the positive edge of one of the block’s output clocks.
1
You must set a variable-step discrete solver in Simulink when you are using multiple
clock domains.
To ensure a proper hardware implementation of a DSP Builder design using multiple
clock domains, consider the following points:
■
Do not use DSP Builder combinational blocks for rate transitions to ensure that the
behavior of the DSP Builder Simulink model is identical to the generated RTL
representation.
Figure 3–8 illustrates an incorrect use of the DSP Builder Logical Bit Operator
(NOT) block.
Figure 3–8. Example of Incorrect Usage: Mixed Sampling Rate on a NOT Block
November 2013
Altera Corporation
DSP Builder Handbook
Volume 2: DSP Builder Standard Blockset
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